Embedded memory devices, such as embedded dynamic random access memory (eDRAM), having deep trench capacitors have demonstrated great advantages over planar-stacked device structures. Trench capacitors have replaced the planar storage capacitors in order to meet the scaling demands for high performance dynamic random access memory (DRAM) cell production.
A trench capacitor is a three-dimensional device formed by etching a trench into a semiconductor substrate. After trench etching, a doped region is typically formed in the lower portion of the trench surrounding interior walls of the trench, which serves as an outer electrode or a buried plate electrode of the trench capacitor. A node dielectric is then formed over the outer or buried plate electrode in the trench, which serves as the insulating layer of the trench capacitor, followed by filling the trench, for example, with doped polycrystalline silicon (hereinafter poly-Si), which serves as the inner or upper electrode of the trench capacitor.
However, the doped poly-Si inner or upper electrode of the conventional trench capacitor as described hereinabove has a relatively high electrical resistivity as compared to metallic electrodes. Further, the conventional trench capacitor in an eDRAM or DRAM device is connected to an adjacent field effect transistor (FET) by an out-diffused buried strap, which is also highly resistive. The highly resistive poly-Si electrode and out-diffused buried strap lead to high parasitic resistance in the eDRAM or DRAM device, which in turn limits the performance of the device. As eDRAM and DRAM technologies are scaled beyond the 65 nm node, the deleterious impact of the highly resistive poly-Si electrode and out-diffused buried strap on the performance of the eDRAM or DRAM cells, especially on the read/write speed of such memory cells, becomes much more significant, because the resistivity of the poly-Si electrode and the out-diffused buried strap does not scale with the remaining components of the eDRAM or DRAM cell.
There is therefore a continuing need for improved trench capacitor structures that can be readily incorporated into the eDRAM or DRAM devices to reduce the parasitic resistance in such devices and to enhance the performance, especially the read/write speed, of such devices.
There is further a need for a method that can readily integrate the processing steps required for fabricating such improved trench capacitor structures into the eDRAM or DRAM device fabrication processes, with little or no deleterious impact on the performance of the transistors that are formed adjacent to the trench capacitor structures in the eDRAM or DRAM devices.